1. Field of the Invention
The invention relates generally to semiconductor devices such as field effect transistor (FET) devices. More particularly, the invention relates to efficient methods for fabricating semiconductor devices, such as field effect transistor devices with enhanced performance.
2. Description of the Related Art
Integrated circuits commonly comprise field effect transistor devices as active switching elements. For purposes of reducing power consumption, field effect transistor devices are typically provided as complementary doped pairs. Various factors affect field effect transistor device performance. Non-limiting examples of such factors include dimensional, materials of composition, mechanical stress effect and doping related factors.
Attention has recently focused upon the gate electrode composition related performance effects when fabricating field effect transistor devices. To that end, field effect transistor devices fabricated with fully silicided gate electrodes are desirable since fully silicided gate electrodes often have enhanced conductivity, and they are not subject to polysilicon dopant depletion phenomena. Fully silicided gate electrodes also have other performance advantages in comparison with other gate electrode materials.
Various field effect transistor structures using suicide gate electrodes, and methods for fabrication thereof, are known in the art.
For example, Xiang et al., in U.S. Pat. No. 6,562,718, teaches a method for fabricating a field effect transistor structure with a fully silicided gate electrode. The method disclosed in the '718 patent uses a shielding layer located upon a pair of silicided source/drain regions, but not a partially silicided gate electrode within the field effect transistor structure, so that the partially silicided gate electrode may be fully silicided without affecting the silicided source/drain regions.
In addition, Gong et al., in U.S. Pat. No. 6,902,994, teaches an additional method for fabricating a field effect transistor structure with a fully silicided gate electrode. The method disclosed in the '994 patent provides for simultaneous silicidation of a pair of raised source/drain regions and a silicon gate electrode after removing a capping layer used to protect the silicon gate electrode when forming the pair of raised source/drain regions.
Further, Lin et al., in U.S. Pat. No. 6,905,922, teaches a method for fabricating dual fully silicided gate electrodes within field effect transistor structures. This prior method uses a protective layer formed upon a pair of silicided source/drain regions when fully siliciding the gate electrodes.
Still further, Wen et al., in U.S. Patent Application Publication 2005/0156238, also teaches a silicided gate field effect transistor structure and a method for fabricating the same. The Wen et al. method provides for protecting a pair of silicided source/drain regions when siliciding a silicon gate electrode within the field effect transistor device.
Finally, Bu et al., in U.S. Patent Application Publication 2005/0215055, also teaches a silicided gate field effect transistor structure and a method for fabricating the same. The Bu et al. method provides for forming a silicided gate electrode prior to a pair of sillicided source/drain regions.
As semiconductor device technology continues to advance, needs continue to exist for fabricating field effect transistor devices with enhanced performance. To that end, desirable are additional field effect transistor structures having silicided gate electrodes, as well as methods for fabrication thereof.